1) Technical Field
Embodiments of the present invention relate to a latency control device and a semiconductor device including the same, and more particularly to a technology for improving a screen-test throughput by controlling latency.
2) Description of the Related Art
Multiple semiconductor devices contained in a system are configured to communicate with each other. For example, if a system controller of a semiconductor memory device such as a DRAM performs a read command, the memory device outputs stored data to a controller.
However, when the memory device receives a read command, the memory device may immediately output data. A predetermined time may be required for the memory device to perform a read command because data is retrieved from the memory device and the retrieved data is arranged and output during the predetermined time.
For mutual operations of multiple semiconductor devices, there is a need to define a standby time in which a specific signal is applied to the semiconductor device and the operation corresponding to the specific signal is then carried out. The standby time is referred to as a latency. For example, a specific time in which a read command is applied to a DRAM and data is then output is referred to as a CAS latency (CL).
Assuming that the CAS latency (CL) is denoted by ‘CL=5 clocks (tCK)’, data should be output through a DQ pad of a DRAM after lapse of 5 clocks starting from a time at which a read command is applied to an input pad of the DRAM. A latency control circuit is configured to adjust a time delay of an input signal in such a manner that an operation corresponding to various signals applied to the semiconductor device can be carried out at an accurate time point in accordance with latency associated with performing the operation.
However, when inputting or outputting data, a synchronous semiconductor device is synchronized with an external clock received from an external part. Accordingly, a conventional latency control circuit operates in synchronization with a clock signal, so that latency is limited to a minimum delay unit of a time period of the clock signal.
In addition, the conventional latency control circuit is coupled in series to a flip-flop so as to successively process a plurality of signals arranged at predetermined time intervals shorter than a maximum delay amount. The conventional latency control circuit is configured to perform a serial shift operation through the flip-flop so as to process contiguous command signals.
Accordingly, a minimum latency delay amount or a maximum latency delay amount is limited to “(clock period)×(number of flip-flops)”. That is, the clock period may correspond to a minimum delay amount, where the minimum delay unit operates in synchronization with the clock signal. In addition, the maximum delay amount is denoted by “(clock period)×(number of flip-flops)”. The above-mentioned characteristics may limit a screen test throughput.